Research Book Chapters
[BC6] – Ishan Thakkar, Supreeth Mysore Shivanandamurthy, Sayed Ahmad Salehi, “Low-Latency, Energy-Efficient In-DRAM CNN Acceleration with Bit-Parallel Unary Computing,” Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer Nature, 2023.
[BC5] – Febin Sunny, Asif Mirza, Ishan Thakkar, Sudeep Pasricha, Mahdi Nikdast, “Improving Energy Efficiency in Silicon Photonic Networks-on-Chip with Approximation Techniques,” Silicon Photonics for High-Performance Computing and Beyond, CRC Press/Taylor & Francis Group, 2021.
[BC4] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Varun Bhat, Sairam Sri Vatsavai, Sudeep Pasricha, “Securing Silicon Photonic NoCs Against Hardware Attacks”, to appear, Springer Book on Network-on-Chip Security and Privacy, 2021.
[BC3] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Varun Bhat, Sairam Sri Vatsavai, Sudeep Pasricha, “Hardware Security in Emerging Photonic Network-on-Chip Architectures,” Silicon Photonics for High-Performance Computing and Beyond, to appear, Springer Book on Emerging Computing, June 2020.
[BC2] – Ishan Thakkar, Sudeep Pasricha, Venkata Sai Praneeth Karempudi, Sai Vineel Reddy Chittamuru, “Exploring Aging Effects in Photonic Interconnects for High-Performance Manycore Architectures,” Silicon Photonics for High-Performance Computing and Beyond, CRC Press/Taylor & Francis Group, to appear in December 2019.
[BC1] - Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan Thakkar, “Enhancing Process Variation Resilience in Photonic NoC Architectures,” Photonic Interconnects for Computer Systems – Understanding and Pushing Design Challenges, River Publishers, June 2017.
Archived Publications
[AP1] - Supreeth Mysore Shivanandamurthy, Ishan Thakkar, Sayed Ahmad Salehi, "ODIN: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM," January 2020.
Peer-Reviewed Journal Publications (Full-Papers)
[J11] – Sairam Sri Vatsavai, Ishan Thakkar, “Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 11, 2022.
[J10] – Amlan Ganguly, Sergi Abadal, Ishan Thakkar, Natalie Enright Jerger, Marc Riedel, Masoud Babaie, Rajeev Balasubramonian, Abu Sebastian, Sudeep Pasricha, Baris Taskin, “Interconnects for DNA, Quantum, In-Memory and Optical Computing: Insights from a Panel Discussion,” IEEE Micro, 2022.
[J9] - Venkata Sai Praneeth Karempudi, Febin Sunny, Ishan G Thakkar, Sai Vineel Reddy Chittamuru, Mahdi Nikdast, Sudeep Pasricha, "Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study," accepted in the ACM Journal on Emerging Technologies in Computing Systems (JETC), 2021.
[J8] - Febin Sunny, Asif Mirza, Ishan Thakkar, Mahdi Nikdast, Sudeep Pasricha, “ARXON: A Framework for Approximate Communication over Photonic Networks-on-Chip”, to appear, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2021.
[J7] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, Sairam Sri Vatsavai, Varun Bhat, “Exploiting Process Variations to Secure Photonic NoC Architectures from Snooping Attacks,” accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
[J6] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, "LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip," accepted for publication in IEEE Transactions on Multi-Scale Computing Systems (TMSCS), June 2018.
[J5] - Ishan Thakkar, Sudeep Pasricha, "DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency and Restorable Endurance," IEEE Transactions on Computer-Aided Design (TCAD), vol. 37, no. 9, pp. 1760-1773, September 2018.
[J4] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, "HYDRA: Heterodyne Crosstalk Mitigation with Double Microring Resonators and Data Encoding for Photonic NoCs," IEEE Transactions on Very Large-Scale Integration (TVLSI), vol. 26, no. 1, pp. 168-181, January 2018.
[J3] - Ishan Thakkar, Sudeep Pasricha, "3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead," IEEE Transactions on Multi-Scale Computing Systems (TMSCS), vol. 1, no. 3, pp. 168-184, September 2015. (Best Paper Candidate)
[J2] - Ishan Thakkar, Sudeep Pasricha, "3D-WiRED: A Novel WIDE I/O DRAM with Energy-Efficient 3-D Bank Organization," IEEE Design & Test, vol. 32, no. 4, pp. 71-80, August 2015.
[J1] - Ishan Thakkar, Kevin L Lear, Jonathan Vickers, Brian Heinze, and Kenneth Reardon, "A plastic total internal reflection photoluminescence device for enzymatic biosensing," Lab Chip, vol. 13, no. 34, pp. 4775-4783, December 2013.
Peer-Reviewed Conference Publications (Full-Papers; 15-30% acceptance rate)
[C35] - Ishan Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, "High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures," ACM Great Lakes Symposium on VLSI (GLSVLSI), June 2023.
[C34] – Sairam Sri Vatsavai, Ishan Thakkar, “A Bit-Parallel Deterministic Stochastic Multiplier,” IEEE International Symposium on Quality Electronic Design (ISQED'23), April 2023.
[C33] – Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan Thakkar, Sayed Ahmad Salehi, “AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning,” IEEE International Symposium on Quality Electronic Design (ISQED'23), April 2023.
[C32] – Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan Thakkar, Jeffrey Todd Hastings, “A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits,” IEEE International Symposium on Quality Electronic Design (ISQED'23), April 2023.
[C31] – Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan Thakkar, “An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks,” IEEE International Symposium on Quality Electronic Design (ISQED'23), April 2023.
[C30] – Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan Thakkar, Jeffrey Todd Hastings, Sayed Ahmad Salehi, “SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs,” IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2023.
[C29] – Venkata Sai Praneeth Karempudi, Ishan Thakkar, Jeffrey Todd Hastings, “A Silicon Nitride Microring Based High-Speed, Tuning-Efficient, Electro-Refractive Modulator,” IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, December 2022.
[C28] – Sairam Sri Vatsavai, Ishan Thakkar, “Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors,” IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2022.
[C27] – Venkata Sai Praneeth Karempudi, Shreyan Datta, Ishan Thakkar, "Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit," ACM Conference on Embedded Networked Sensor Systems (SenSys) 2021.
[C26] - Supreeth Mysore Shivanandamurthy, Ishan Thakkar, Sayed Ahmad Salehi, "ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021. [pre-print] (Best Paper Award Nominee)
[C25] - Bobby Bose, Ishan Thakkar, "Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs," ACM Great Lakes Symposium on VLSI (GLSVLSI), June 2021. (Best Paper Award)
[C24] - Sairam Sri Vatsavai, Ishan Thakkar, "Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing," IEEE 34th International Conference on VLSI Design & 20th International Conference on Embedded Systems (VLSID 2021), February 2021.
[C23] - Chao-Hsuan Huang, Ishan Thakkar, "Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration," IEEE International Conference on Computer Design (ICCD), October 2020.
[C22] - Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan Thakkar, "PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance," IEEE/ACM International Symposium on Networks-on-Chip (NOCS), September 2020.
[C21] - Febin Sunny, Asif Mirza, Ishan Thakkar, Sudeep Pasricha, Mahdi Nikdast, "LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip," ACM Great Lakes Symposium on VLSI (GLSVLSI), September 2020. [pre-print] (Best Paper Award Honorable Selection)
[C20] - Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan Thakkar, "Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication," ACM Great Lakes Symposium on VLSI (GLSVLSI), September 2020. [pre-print]
[C19] - Venkata Sai Praneeth Karempudi, Ishan Thakkar, "Mitigating Inter-Channel Crosstalk Non-Uniformity in Microring Filter Arrays of Wavelength-Multiplexed Photonic NoCs," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA, October 2019.
[C18] - Supreeth Mysore Shivanandamurthy, Ishan Thakkar, Sayed Ahmad Salehi, "A Scalable Stochastic Number Generator for Phase Change Memory Based In-Memory Stochastic Processing," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA, October 2019.
[C17] - Chao-Hsuan Huang, Ishan Thakkar, "Mitigating Write Disturbance in Phase Change Memory," ACM/IEEE International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems (CASES), New York, NY, USA, October 2019.
[C16] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling," IEEE Workshop on Energy-efficient Networks of Computers (E2NC): from the Chip to the Cloud, Pittsburgh, PA, USA, October 2018.
[C15] - Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan Thakkar, Varun Bhat, "Securing Photonic NoCs from Hardware Trojans," IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Torino, Italy, October 2018.
[C14] - Sudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan Thakkar, "Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip," ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, USA, May 2018.
[C13] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Varun Bhat, Sudeep Pasricha, "SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures," IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, June 2018. (acceptance rate: 168/691 = 24.3%)
[C12] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling," IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Seoul, South Korea, October 2017. (acceptance rate: 14/44 = 31.8%)
[C11] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, "Analyzing Voltage Bias and Temperature Induced Aging Effects in Photonic Interconnects for Manycore Computing," ACM System Level Interconnect Prediction Workshop (SLIP), Austin, TX, USA, June 2017.
[C10] - Ishan Thakkar, Sudeep Pasricha, "DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency," IEEE International Conference on VLSI Design (VLSID), Hyderabad, India, January 2017. (acceptance rate: 71/292 = 24.3%)
[C9] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Pittsburgh, PA, USA, October 2016. (acceptance rate: 21/80 = 26.3%)
[C8] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers," IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Nara, Japan, August 2016.
[C7] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects," ACM System Level Interconnect Prediction Workshop (SLIP), Austin, TX, USA, June 2016. (Best Paper Award)
[C6] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, "PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs," IEEE/ACM Design Automation Conference (DAC), Austin, TX, USA, June 2016. (acceptance rate: 152/876=17%)
[C5] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, "Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures," IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, March 2016. (acceptance rate: 36.3%) (Best Paper Award Finalist)
[C4] - Ishan Thakkar, Sudeep Pasricha, "Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures," IEEE International Conference on VLSI Design (VLSID), Kolkata, India, January 2016. (acceptance rate: 86/339 = 25.4%)
[C3] - Ishan Thakkar, Sudeep Pasricha, "A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses," IEEE International Conference on Computer Design (ICCD), New York, NY, USA, Oct 2015. (acceptance rate: 83/269=30.8%)
[C2] - Sudeep Pasricha, Ishan Thakkar, "Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces," Memory Architecture and Organization Workshop (MeAOW), Oct 2014.
[C1] - Ishan Thakkar, Sudeep Pasricha, "3D-Wiz: A Novel High Bandwidth, Optically Interfaced 3D DRAM Architecture with Reduced Random Access Time," IEEE International Conference on Computer Design (ICCD), Seoul, South Korea, Oct 2014. (acceptance rate: 64/207=30.9%)
Invited Seminar/Conference Talks
[T7] - Ishan Thakkar, “VBTI Aging: Yet Another Critical Design Challenge for Microring Resonator Based Silicon Photonic Interconnects,” Silicon Photonics for High-Performance Computing Workshop (SPHPC), Fort Collins, CO, USA, May 2018.
[T6] - Ishan Thakkar, “Design and Optimization of Interconnection and Memory Subsystems for Future Manycore Computing,” Department of Electrical and Computer Engineering, University of Massachusetts Dartmouth, Dartmouth, MA, USA, April 2018.
[T5] - Ishan Thakkar, “Design and Optimization of Interconnection and Memory Subsystems for Future Manycore Computing,” Department of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA, March 2018.
[T4] - Ishan Thakkar, “Design and Optimization of Interconnection and Memory Subsystems for Future Manycore Computing,” Department of Electrical and Computer Engineering, University of Kentucky, Lexington, KY, USA, February 2018.
[T3] - Ishan Thakkar, “Design and Optimization of Interconnection and Memory Subsystems for Future Manycore Computing,” Computer Engineering, Rochester Institute of Technology, Rochester, NY, USA, February 2018.
[T2] – Ishan Thakkar, “Design and Optimization of Interconnection and Memory Subsystems for Future Manycore Computing,” Department of Electrical Engineering and Computer Science, University of Kansas, Lawrence, KS, USA, December 2017.
[T1] - Sudeep Pasricha, Ishan Thakkar, “Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces,” Memory Architecture and Organization Workshop (MeAOW), October, 2014.
Conference Poster Presentations
[CP8] - Venkata Sai Praneeth Karempudi, Ishan Thakkar, "Mitigating Inter-Channel Crosstalk Non-Uniformity in Microring Filter Arrays of Wavelength-Multiplexed Photonic NoCs," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA, October 2019.
[CP7] - Supreeth Mysore Shivanandamurthy, Ishan Thakkar, Sayed Ahmad Salehi, "A Scalable Stochastic Number Generator for Phase Change Memory Based In-Memory Stochastic Processing," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA, October 2019.
[CP6] - Chao-Hsuan Huang, Ishan Thakkar, "Mitigating Write Disturbance in Phase Change Memory," ACM/IEEE International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems (CASES), New York, NY, USA, October 2019.
[CP5] - Ishan Thakkar, “Design and Optimization of Emerging Network-Memory Subsystems for Future Manycore Architectures,” in PhD Forum at the ACM/IEEE Design Automation Conference (DAC), Austin, TX, USA, June 2017.
[CP4] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling," ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Pittsburgh, PA, USA, October 2016.
[CP3] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, “Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Nara, Japan, August 2016.
[CP2] - Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs,” IEEE/ACM Design Automation Conference (DAC), Austin, TX, USA, June 2016.
[CP1] - Ishan Thakkar, Sudeep Pasricha, “A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses,” IEEE International Conference on Computer Design (ICCD), New York, NY, USA, October 2015.
Research Posters (Non-Conference)
[P3] – Chao-Hsuan Huang, Ishan Thakkar, “Mitigating Write Disturbance in Phase Change Memory Architectures,” ECE Research Symposium, University of Kentucky, Lexington, KY, USA, April 2019.
[P2] - Ishan Thakkar, Sai Vineel Reddy Chittamuru, Sudeep Pasricha, “A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects,” ACM/IEEE Design Automation Conference Work in Progress (WIP), Austin, TX, USA, June 2016.
[P1] - Ishan Thakkar, Sudeep Pasricha, “Improving the Performance and Power Efficiency of Memory with 3D Stacking and High-Bandwidth Optical Interfacing,” CSU Ventures Innovation Forum, Fort Collis, CO, USA, April 2016.
Patents Submitted
[PAT2] - U.S. provisional patent application serial no. 16/434420, titled “Hardware Security for Photonic Communication Architectures,” filed on 6/7/2019.
Inventors: Sai Vineel Reddy Chittamuru, Sudeep Pasricha, Ishan Thakkar
[PAT1] - U.S. provisional patent application serial no. 61/970,155, titled “Low Cost Chemical and Biochemical Sensor,” filed on 3/25/14.
Inventors: Ishan Thakkar, Kevin L Lear, Kenneth F Reardo