My research broadly focuses on the design and optimization of unconventional (more-than-Moore) architectures and technologies for energy-efficient, reliable, and secure computing, for a wide scope of platforms including embedded systems, internet-of-things (IoT), and high-performance computing systems. More specific more-than-Moore technology interests include (1) Silicon photonics; (2) Optical computing; (3) Neuromorphic computing; (4) In-memory computing; (5) Stochastic computing; (6) Monolithic 3D (M3D) integration; (7) Polymer and transparent conductive oxides based photonic devices and sensors. 

Citations and publications are listed at: [Google Scholar] [DBLP]

List of Past and Ongoing Research Projects:

• Extreme-Scale Optical Computing (Beyond Petascale/Chip Performance)
  • Design of neuromorphic optical hardware accelerators (selected publications: [C35], [C31], [C30], [C28], [C24], [J11])
  • Design and optimization of highly scalable photonic integrated circuits (PICs) and systems (selected publications: [C35], [C32], [C27], [C20], [C12], [C7])
• In-Memory Computing
  • In-memory accelerators for deep learning (selected publications: [C33], [C26], [C25], [AP1])
• Data Communication Security in Manycore Architectures 
  • Hardware security with photonic NoCs (selected publications: [C15], [C13], [J7])
• Bit-Parallel Stochastic Computing
  • Highly scalable and error-resilient stochastic circuits with precision-independent latency (selected publications: [C34], [C26], [AP1], [C18])
• Optoelectronic/Photonic Devices and Sensors
  • High-speed electro-photonic devices (selected publications: [C32], [C29])
  • Polymer-based photonic biosensors (selected publications: [J1])
• Self-Adaptive Photonic Interconnects for Manycore Computing
  • Adaptive data approximations for dynamic savings in static power consumption (selected publications: [C21], [J8]) 
  • Cognitive circuit-level and link-level reconfigurations to improve reliability and energy efficiency under context variations (fabrication process, temperature, optical losses, and aging variations) (selected publications: [C22], [C16], [C14], [C9], [J6])
  • Crosstalk noise analysis and mitigation (selected publications: [C19], [C9], [C6], [C5], [J9], [J4]) 
• Emerging Memory Technologies and Architectures
  • Fine-grained TSVs based 3D-folded DRAM architectures (selected publications: [C3], [C1], [J3], [J2])
  • Latency, reliability, and lifetime optimizations for emerging nonvolatile memory architectures (selected publications: [C25], [C17], [C10], [J5])  
  • Optical interfacing for high-speed memories (selected publications: [C1], [J3])
  • Monolithic 3D (M3D) integrated memory architectures (selected publications: [C23])

Research Sponsors and Collaborators: